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Traditionally synthesis methods of combinatorial circuits on PLD include next stages:

Creating general model PLD with using classical methods of synthesis;
Solving classical tasks of synthesis for the given model (minimization, decomposition, a factorization etc.), and such tasks may be several;
Mapping the obtained logic circuit on structure real PLD.

Disadvantages of the given approach consist in the following:

It is used too general model PLD which does not allow to use all architectural features real PLD;
Classical tasks of synthesis do not allow to take into account the majority of architectural features PLD, therefore even exact solutions of classical tasks of the synthesis, realizable on PLD, are not optimal;
As, as a rule, during synthesis it is necessary to solve several classical tasks at passage from one of them to another errors may be brought in obtained result;
Features of solution of the task of mapping of the logic circuit on physical structure PLD are not taken into account, therefore frequently at this stage it is necessary to solve again tasks of minimization, decomposition etc.

Main differences of the offered approach to synthesis of combinatorial circuits on PLD from traditional consist in the following:

It is defined not one, but three models of PLD: universal PAL (Programmable Array Logic), 'classical' PAL and CPLD (Complex PLD), and each model most effectively allows to take into account architectural features of the appropriate class PLD;
For the most effective application of an appropriate method of synthesis preliminary conversion of the initial system of Boolean functions is carried out; Methods of synthesis take the most of architectural possibilities of modern PLD;
The task of mapping of the synthesized combinatorial circuit on structure PLD in part or completely is solved during synthesis.

The reduction of implementation costs of combinatorial circuits in offered synthesis methods is achieved due to an effective utilization of the following architectural features PLD:

Possibilities to program of a logical level of output signals;
it allows to realize simple representation of each function: direct or inverse;
Internal feedback chains; it allows value of already realized functions and their inversions to use as factors for implementation of other functions;
Macrocells with two feedbacks; it allows simultaneously to accept values of input variables and to realize intermediate functions by one macrocell PLD;
Possibilities to connect of various number of product terms to various macrocells PLD etc.

All considered methods include a stage of preliminary conversion of the original Boolean Function System and creation of set Y* of realizable functions for the most effective application of an appropriate synthesis method.