Free-of-charge
services
The
Given section is open for the help in mastering by practical
developers of new approaches to designing digital systems with the
help of ZUBR.
If it is necessary for you
to optimize the project by deprecication
and rises of speed developers of ZUBR package completely
free-of-charge will help you with mastering new methods of
synthesis. For this purpose it is enough to select(allocate) those
parts which represent combinatorial circuits and - or finite state
automations in the project to describe them in the source language of
ZUBR (see. 1 applications and 2) and to send appropriate text files
(by association to accompanying letter) to the address of the e-mail
of ZUBR:
zubr@ii.pb.bialystok.pl.
In the covering letter do
not overlook to specify, please,
- The set PLD (with the
instruction(indication) of the corporation - manufacturer), and also a
concrete used chip;
- Method of synthesis (see section
"methods of synthesis");
- The format of output data (VHDL,
Verilog, Abel or AHDL);
- And also some informations about itself
(first name, middle initial, last name, a place of operation, a post,
the contact address);
- And brief performance of the project in
which the given combinatorial circuits or finite state automations (a
title of the project, area of its application) will be used.
In some
days you receive outcomes of synthesis of combinatorial circuits and
finite state automations in the languages of designing indicated by
you with guidelines on their further usage.
1 application. An example of exposition of the
combinatorial circuit
.i 7 -
number of inputs
.o 2 -
number of outputs
.p 9 -
number of strings(lines) in tabulared representation of the system of
functions
-1 - 1 - 10 - an entry vector, through a gap
appropriate
1-11 ---10 an output vector
-001
---10
01
---1-10
-0
- 0 - 01
1
---0 - 01
0
-----0 01
01
- 1 - 01
10-0
---01
.e - the
extremity of exposition
2 application. An example of exposition of the
finite
state automation
.i 3 -
number of inputs
.o 5 -
number of outputs
.p 10 -
number of table lines of passages
.s
4 - number of inwardnesses
0 - S1 S1
00010 - exposition of passage: an entry vector, an initial state,
-0-S1 S1
00010 a state of passage, an output vector
11-S1
S2 10010
-
0 S2 S2 00110
-
1 S2 S3 10110
10-S3
S3 01000
0
- S3 S4 11000
-1-S3
S4 11000
-
0 S4 S4 01001
-
1 S4 S1 11001
.e - the
extremity of exposition
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